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motorola semiconductor technical data ? motorola, inc. 2004 document order number: mc33886/d rev 6.0, 03/2004 33886 simplified application diagram motor 33886 mcu 5.0 v v+ c cp in1 in2 d1 d2 fs out1 out2 pgnd out out out out agnd in v+ 5.0 a h-bridge the 33886 is a monolithic h-bridge ideal for fractional horsepower dc-motor and bi-directional thrust solenoid control. the ic incorporates internal control logic, charge pump, gate drive, and low r ds(on) mosfet output circuitry. the 33886 is able to control continuous inductive dc load currents up to 5.0 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 10 khz. a fault status output reports undervoltage, short circuit, and overtemperature conditions. two independent inputs control the two half- bridge totem-pole outputs. two disabl e inputs force the h-bridge outputs to tri-state (exhibit high impedance). the 33886 is parametrically specif ied over a temper ature range of -40 c t a 125 c, 5.0 v v+ 28 v. the ic can also be operated up to 40 v with derating of the specifications. the ic is available in a surface mount power package with exposed pad for heatsinking. features ? similar to the mc33186dh1 with enhanced features ? 5.0 v to 40 v continuous operation ? 120 m ? r ds(on) h-bridge mosfets ? ttl /cmos compatible inputs ? pwm frequencies up to 10 khz ? active current limiting via internal constant off-time pwm (with temperature-dependent threshold reduction) ? output short circuit protection ? undervoltage shutdown ? fault status reporting ? pb-free packaging designated by suffix code vw 5.0 a h-bridge ordering information device temperature range (t a ) package mc33886dh/r2 -40c to 125c 20 hsop MC33886VW/r2 dh suffix vw (pb-free) suffix case 979c-02 20-terminal hsop 33886 simplified application diagram 33886 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 2 figure 1. 33886 simplified internal block diagram charge pump over- temperature 5.0 v regulator gate drive cur rent li mit, overcurrent sense ci rc uit undervoltage out1 out2 in1 in2 d1 d2 fs c cp v pwr pgnd agnd control logic 80 ua (each) 25 ua 80 a 25 a current limit, short circuit sense circuit charge pump 5.0 v regulator gate drive over- temperature undervoltage v+ c cp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 3 terminal functio n description terminal terminal name formal name definition 1 agnd analog ground low-current analog signal ground. 2 fs fault status for h-bridge open drain active low fault status output requiring a pull-up resistor to 5.0 v. 3 in1 logic input control 1 true logic input control of out1 (i.e ., in1 logic high = out1 logic high). 4, 5, 16 v + positive power supply positive supply connections. 6, 7 out1 h-bridge output 1 output 1 of h-bridge. 8, 20 dnc do not connect either do not connect (leave floating) or connect these terminals to ground in the application. they are test mode te rminals used in manufacturing only. 9?12 pgnd power ground device high-current power ground. 13 d2 disable 2 active low input used to simultaneously tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 14, 15 out2 h-bridge output 2 output 2 of h-bridge. 17 c cp charge pump capacitor external reservoir capacit or connection for internal charge pump capacitor. 18 d1 disable 1 active high input used to simultaneously tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 19 in2 logic input control 2 true logic input control of out2 (i.e ., in2 logic high = out2 logic high). dnc agnd in2 d1 c cp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 dnc pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 4 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit supply voltage v+ 40 v input voltage (note 1) v in -0.1 to 7.0 v fs status output (note 2) v fs 7.0 v continuous current (note 3) i out 5.0 a esd voltage for dh package human body model (note 4) machine model (note 5) v esd1 v esd2 2000 (note 6) 200 v esd voltage for vw package human body model (note 4) machine model (note 5) v esd1 v esd2 2000 200 v storage temperature t stg -65 to 150 c ambient operating temperature (note 7) t a -40 to 125 c operating junction temperature t j -40 to 150 c terminal soldering temperature (note 8) dh suffix vw (pb-free suffix) t solder 220 260 c approximate junction-to-board thermal resistance (and package dissipation = 6.0 w) (note 9) r jb ~5.0 c/w notes 1. exceeding the input voltage on in1, in2, d1, or d2 may cause a malfunction or permanent damage to the device. 2. exceeding the pull-up resistor voltage on the open drain fs terminal may cause permanent damage to the device. 3. continuous current capability so lo ng as junction temperature is 150 c. 4. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 5. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 6. all terminals are capable of human body m odel esd voltages of 2000 v with two exc eptions pertaining only to the dh suffix pac kage: (1) d2 to pgnd is capable of 1500 v and (2) out1 to agnd is capable of 1000 v. 7. the limiting factor is junction temperat ure, taking into account the power dissipat ion, thermal resistance, and heatsinking. 8. terminal soldering temperature limit is for 10 seconds maxi mum duration. not designed for i mmersion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device. 9. exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thickness and composition and copper trace. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 5 static electrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power supply operating voltage range (note 10) v+ 5.0 ? 40 v standby supply current v en = 5.0 v, i out = 0 a i q(standby) ??20 ma threshold supply voltage switch-off switch-on hysteresis v+ (thres-off) v+ (thres-on) v+ (hys) 4.15 4.5 150 4.4 4.75 ? 4.65 5.0 ? v v mv charge pump charge pump voltage v+ = 5.0 v 8.0 v v+ 40 v v cp -v+ 3.35 ? ? ? ? 20 v control inputs input voltage (in1, in2, d1, d2 ) threshold high threshold low hysteresis v ih v il v hys 3.5 ? 0.7 ? ? 1.0 ? 1.4 ? v input current (in1, in2, d1) (note 11) v in = 0 v i in -200 -80 ? a d2 input current (note 12) v d2 = 5.0 v i d2 ?25100 a notes 10. specifications are characte rized over the range of 5.0 v v+ 28 v. operation >28 v will cause some parameters to exceed listed min/max values. refer to typical operating curves to extrapolate values for operation >28 v but 40 v. 11. inputs in1, in2, and d1 have independent internal pull-up current sources. 12. the d2 input incorporates an active internal pull-down current sink. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 6 static electrical charac teristics (continued) characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. ty pical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power outputs (out1, out2) output-on resistance (note 13) 5.0 v v+ 28 v, t j = 25c 8.0 v v+ 28 v, t j = 150c 5.0 v v+ 8.0 v, t j = 150c r ds(on) ? ? ? 120 ? ? ? 225 300 m ? active current limiting th reshold (via internal constant off-time pwm) (note 14) i lim 5.2 6.5 7.8 a high-side short circuit detection threshold i sch 11 ? ? a low-side short circuit detection threshold i scl 8.0 ? ? a leakage current (note 15) v out = v+ v out = gnd i out(leak) ? ? 100 30 200 60 a output fet body diode forward voltage drop (note 16) i out = 3.0 a v f ??2.0 v switch-off thermal shutdown hysteresis t lim t hys 175 ? ? 15 ? ? c fault status (note 17) fault status leakage current (note 18) v fs = 5.0 v i fs (leak) ??10 a fault status set voltage (note 19) i fs = 300 a v fs (low) ??1.0 v notes 13. output-on resistance as measured from output to v+ and ground. 14. product with date codes of december 2002, week 51, will exhibi t the values indicated in this table. product with earlier dat e codes may exhibit a minimum of 6.0 a and a maximum of 8.5 a. 15. outputs switched off with d1 or d2 . 16. parameter is guaranteed by design but not production tested. 17. fault status output is an open drain output requiring a pull-up resistor to 5.0 v. 18. fault status leakage current is measured with fault status high and not set. 19. fault status set voltage is measured with fault status low and set with i fs = 300 a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 7 dynamic electrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (note 20) f pwm ??10khz maximum switching frequency during active current limiting (note 21) f max ??20khz output on delay (note 22) v+ = 14 v t d (on) ??18 s output off delay (note 22) v+ = 14 v t d(off) ??18 s output rise and fall time (note 23) v+ = 14 v, i out = 3.0 a t f , t r 2.0 5.0 8.0 s output latch-off time t a 15 20.5 26 s output blanking time t b 12 16.5 21 s output fet body diode reverse recovery time (note 24) t rr 100 ? ? ns disable delay time (note 25) t d(disable) ??8.0 s short circuit/overtemperature turn- off time (note 26) t fault ?4.0? s power-off delay time t pod ?1.05.0ms notes 20. the outputs can be pwm controlled from an external source. this is typically done by holding one input high while applying a pwm pulse train to the other input. the maximum pwm frequency obtainable is a compromise between switching losses and switching frequency . refer to typical switching waveforms, figures 11 through 18 , pp. 12?13. 21. the maximum switching frequency during active current limiting is internally implem ented. the internal control produces a co nstant off- time pwm of the output. the output load current effects the maximum switching frequency. 22. output delay is the time duration from the midpoint of the in1 or in2 input signal to the 10% or 90% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transit ioning high-to-low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. if the ou tput is transitioning low-to-high, the delay is from the midpoint of the input si gnal to the 10% point of the output response signal. see figure 2 , page 8. 23. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal. see figure 4 , page 8. 24. parameter is guaranteed by design but not production tested. 25. disable delay time is the time duration from the midpoint of the d (disable) input signal to 10% of the output tri-state res ponse. see figure 3 , page 8. 26. increasing currents will become limited at i lim . hard shorts will breach the i sch or i scl limit, forcing the output into an immediate tri-state latch-off. see figures 6 and 7 , page 9. active current limiting wi ll cause junction temperatures to rise. a junction temperature above 160 c will cause the active current limiti ng to progressively "fold back" (or decrease) to 2.5 a typical at 175 c where thermal latch-off will occur. see figure 5 , page 8. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 8 timing diagrams figure 2. output delay time figure 3. disable delay time figure 4. output switching time figure 5. active current limiting versus temperature (typical) time 0 5.0 0 v pwr t d(on) 50% 90% 50% 10% v i n 1 , i n 2 ( v ) t d(off) v o u t 1 , 2 ( v ) ? 0 v 5.0 v 0 ? t r 0 v pwr 90% 10% v o u t 1 , 2 ( v ) 10% 90% t f i m a x , o u t p u t c u r r e n t ( a ) 6.6 2.5 160 175 thermal shutdown t j , junction temperature ( o c) i lim , 6.5 i lim , current (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 9 figure 6. active curren t limiting versus time figure 7. active curre nt limiting detail d 1 , l o g i c i n [0] [1] hard short detect and latch-off typ. short ckt. detect threshold pwm current limiting (see figure 6) 8.0 6.5 i l o a d , o u t p u t c u r r e n t ( a ) f s , l o g i c o u t ou tp ut s tristated t i m e d 2 , l o g i c i n [0] [0] [1] [1] i n n , l o g i c i n [0] [1] in1 in2 in2 in1 out puts operat ional (per input control condition) 0 typ. current limit threshold outputs tristated in2 in1 or or in1 or in2 in2 or in1 diode reverse rec overy spike s (see figure 7) i scl short circuit detect threshold for low-side fets typical current limiting threshold load capacitance and/or diode reverse recovery spikes hard short detect and latch-off in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 outputs tri-stated outputs tri-stated outputs operational (per input control condition) sf i out , active current limiting (see figure 7) i out , current (a) overcurrent minimum threshold t a t b 8.0 time i l o a d , o u t p u t c u r r e n t ( a ) typical pwm load current limiting waveform hard output short latch-off t a = tristate output off time t b = current limit blank time 6.5 hard short detect latch-off prevented during t b short circuit detect threshold t a = output latch-off time t b = output blanking time i scl short circuit detect threshold i out , current (a) typical current limiting waveform f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 10 electrical performance curves figure 8. typical high-side r ds(on) versus v+ figure 9. typical low-side r ds(on) versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 volts ohms 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.13 0.128 0.126 0.124 0.122 0.12 ohms v pwr ohms volts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 11 figure 10. typical quiescent supply current versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 5.0 4.0 3.0 2.0 1.0 0.0 ohms v pwr 6.0 7.0 8.0 9.0 milliamperes volts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 12 typical switching waveforms important for all plots, the following applies: ? ch2=2.0 a per division ?l load =533 h @ 1.0 khz ?l load =530 h @ 10.0 khz ?r load =4.0 ? figure 11. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 10% figure 12. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 50% figure 13. output voltage and current vs. input voltage at v+ = 34 v, pmw frequency of 1.0 khz, and duty cycle of 90%, showing device in current limiting mode figure 14. output voltage and current vs. input voltage at v+ = 22 v, pmw frequency of 1.0 khz, and duty cycle of 90% v+=24 v f pwm =1.0 khz duty cycle=10% i out output voltage (out1) input voltage (in1) v+=24 v f pwm =1.0 khz duty cycle=50% i out output voltage (out1) input voltage (in1) v+=34 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=22 v f pwm =1.0 khz duty cycle=90% i out output voltage (out1) input voltage (in1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 13 figure 15. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 50% figure 16. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 90% figure 17. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 50% for a purely resistive load figure 18. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 90% for a purely resistive load v+=24 v f pwm =10 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=24 v f pwm =10 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=90% output voltage (out1) i out input voltage (in1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 14 table 1. truth table the tri-state conditions and the faul t status are reset using d1 or d2 . the truth table uses the following notations: l = low, h = high, x = high or low, and z = high impedance (all output power transistors are switched off). device state input conditions fault status flag output states d1 d2 in1 in2 fs out1 out2 forward l h h l h h l reverse l h l h h l h freewheeling low l h l l h l l freewheeling high l h h h h h h disable 1 (d1) h x x x l z z disable 2 (d2 )xlxxlzz in1 disconnected l h z x h h x in2 disconnected l h x z h x h d1 disconnected z x x x l z z d2 disconnected x z x x l z z undervoltage (note 27) x x x x l z z overtemperature (note 28) x x x x l z z short circuit (note 28) x x x x l z z notes 27. in the case of an undervoltage condition, the outputs tri-stat e and the fault status is set logic low. upon undervoltage rec overy, fault status is reset automatically or automatically cleared and the ou tputs are restored to their original operating condition. 28. when a short circuit or overtemperatur e condition is detected, the power outputs are tri-state latched-off independent of th e input signals and the fault status flag is set logic low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 15 system/application information introduction numerous protection and operational features (speed, torque, direction, dynamic braking, and pwm control), in addition to the 5.0 a current c apability, make the 33886 a very attractive, cost-effective solution for controlling a broad range of fractional horsepower dc motors. a pair of 33886 devices can be used to control bipolar stepper motors in both directions. in addition, the 33886 can be used to control permanent magnet solenoids in a push-pull variable force fashion using pwm control. the 33886 can also be used to excite transformer primary windings with a switc hed square wave to produce secondary winding ac currents. as shown in figure 1 , simplified internal block diagram, page 2, the 33886 is a fully prot ected monolithic h-bridge with fault status reporting. for a dc motor to run the input conditions need be as follows: d1 input logic low, d2 input logic high, fs flag cleared (logic high), with one in logic low and the other in logic high to define output polarity. the 33886 can execute dynamic braking by simultaneously turning on either both high-side mosfets or both low- side mosfets in the output h-bridge; e.g., in1 and in2 logic high or in1 and in2 logic low. the 33886 outputs are capable of providing a continuous dc load current of 5.0 a from a 40 v v+ source. an internal charge pump supports pwm frequencies up to 10 khz. an external pull-up resistor is required for the open drain fs terminal for fault status reporting. two independent inputs (in1 and in2) provide control of the two totem-pole half-bridge outputs. two disable inputs (d1 and d2 ) are for forcing the h-bridge outputs to a high impedance state (all h-bridge switches off). the 33886 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch-off, and overtemperature latch-off. an undervoltage shutdown, output short circuit latch-off, or overtemperature latch-off fault condition will cause the outputs to turn off (i.e., become high impedance or tri-stated) and t he fault output flag to be set low. either of the disable inpu ts or v+ must be ?toggled? to clear the fault flag. the short circuit/overtemperature shutdown scheme is unique and best described as using a junction temperature- dependent active current ?fold back? protection scheme. when a short circuit condition is experienced, the current limited output is ?ramped down? as the junction temperature increases above 160 c, until at 175 c the current has decreased to about 2.5 a. above 175 c, overtemperature shutdown (latch-off) occurs. this feature allows the device to remain in operation for a longer time with unexpected loads, while still retaining adequate protection for both the device and the load. functional terminal description pgnd and agnd power and analog ground terminals. the power and analog ground terminals should be connec ted together with a very low impedance connection. v+ v+ terminals are the power supply inputs to the device. all v+ terminals must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between terminals. v+ terminals have an undervoltage threshold. if the supply voltage drops below a v+ undervol tage threshold, the output power stage switches to a tri-stat e condition and the fault status flag is set and the fault status terminal voltage switched to a logic low. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to t he established condition of the input terminals and the fault stat us flag is automatically reset logic high. fault status (fs ) this terminal is the device fault status output. th is output is an active low open drain structure requiring a pull-up resistor to 5.0 v. refer to table 1, truth table , page 14. in1, in2, d1, and d2 these terminals are input contro l terminals used to control the outputs. these terminals are 5.0 v cmos-compatible inputs with hysteresis. the in 1 and in2 independently control out1 and out2, respectively. d1 and d2 are complimentary inputs used to tri-state disable the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tri- state disabled; however, the rest of the device circuitry is fully operational and the supply i q(standby) current is reduced to a few milliamperes. refer to table 1, truth table , and static electrical characteristics table, page 5. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 16 out1 and out2 these terminals are the out puts of the h-bridge with integrated output fet body diodes. the bridge output is controlled using the in1, in2, d1, and d2 inputs. the outputs have active current limiting abov e 6.5 a. the outputs also have thermal shutdown (tri-state latc h-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) incorporated to detect currents that are higher than active current limit is activated at each output activation to facilitate detecti ng hard output short conditions (see figure 7 , page 9). c cp charge pump output terminal. a filter capacitor (up to 33 nf) can be connected from the c cp terminal and pgnd. the device can operate without t he external capacitor, although the c cp capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and pwm frequency. performance features short circuit protection if an output short circuit condition is detected, the power outputs tri-state (latch-off) in dependent of the input (in1 and in2) states, and the fault status output flag is set logic low. if the d1 input changes from logic high to logic low, or if the d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input terminals (in1, in2, d1, and d2 ), provided the device junction temperature is wit hin the specified operating temperature. active current limiting the maximum current flow under normal operating conditions is internally limited to i lim (5.2 a to 7.8 a). when the maximum current value is reache d, the output stages are tri- stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated with th e load characteristics, the current decreases during the tr i-state duration until the next output on cycle occurs (see figures 7 and 13 , page 9 and page 12, respectively). the current limiting threshold value is dependent upon the device junction temperature. when -40 c < t j < 160 c, i lim is between 5.2 a and 7.8 a. when t j exceeds 160 c, the i lim current decreases linearly down to 2.5 a typical at 175 c. above 175 c the device overtemperature circuit detects t lim and overtemperature shutdown occurs (see figure 5 , page 8). this feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160 c. overtemperature shutdown and hysteresis if an overtemperature conditi on occurs, the power outputs are tri-state (latched-off) ind ependent of the input signals and the fault status flag is set logic low. to reset from this condition, d1 must change from logic high to logic low, or d2 must change from logic low to logic high. when reset, the output stage s witches on again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. note resetting from the fault condition will clear the fault status flag. main differences compared to mc33186dh1 ? cod terminal has been removed. terminal 8 is now a do not connect (dnc) terminal. ? terminal 20 is no longer connected in the 20 hsop package. it is now a dnc terminal. ?r ds(on) max at t j = 150c is now 225 m ? per each output transistor. ? maximum temperature opera tion is now 160c, as minimum thermal shutdown temperature has increased. ? current regulation limiting foldback is implemented above 160c t j . ? thermal resistance junction to case has been increased from ~2.0c/w to ~5.0c/w. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 17 package information the 33886 is designed for enhanced thermal performance. the significant feature of this de vice is the exposed copper pad on which the power die is soldered. this pad is soldered on a pcb to provide heat flow to ambient and also to provide thermal capacitance. the more copper area on the pcb, the better the power dissipation and transient behavior will be. example characterization on a double-sided pcb: bottom side area of copper is 7.8 cm 2 ; top surface is 2.7 cm 2 (see figure 19 ); grid array of 24 vias 0.3 mm in diameter. figure 19. pcb test layout figure 20 shows the thermal response with the device soldered on to the test pcb described in figure 19 . figure 20. 33886 thermal response top side bottom side 0,1 1 10 100 0,001 0,01 0,1 1 10 100 1000 10000 t, time (s) rth (c/w) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33886 motorola analog integrated circuit device data 18 applications a typical application schematic is shown in figure 21 . for precision high-current applic ations in harsh, noisy environments, the v+ by-pass capacitor may need to be substantially larger. figure 21. 33886 typical application schematic motor agnd out1 pgnd v+ c cp out2 d2 d1 fs in1 in2 33 nf 47 f v+ 33886 + in2 in1 fs d1 d2 dc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33886 19 package dimensions dh suffix vw (pb-free) suffix 20-terminal hsop plastic package case 979c-02 issue a seating plane datum plane bottom view a x 45 e1 e d h e 18x b m bbb c 20 11 10 1 e2 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane -h-. 5. dimension b does not incl ude dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums -a- and -b- to be determined at datum plane -h-. 7. dimension d does not i nclude tiebar protrusions. allowable tiebar protrusions are 0.150 per side. d2 d1 e3 a2 section w-w b c1 b1 c e4 a m aaa c exposed heatsink area a b c h pin one id 10x y gauge plane detail y (1.600) l w w q bbb c l1 a1 a3 dim min max millimeters a 3.000 3.400 a1 0.100 0.300 a2 2.900 3.100 a3 0.00 0.100 d 15.800 16.000 d1 11.700 12.600 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 6.400 7.200 e4 2.700 2.900 l 0.840 1.100 l1 0.350 bsc b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 bsc h --- 1.100 q 0 8 aaa 0.200 bbb 0.100 e/2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 minami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h. k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc33886/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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